1. Technical Field of the Invention
The present invention relates to redundancy circuitry for semiconductor memory devices, and particularly to row/column redundancy circuitry for random access memory (RAM) devices.
2. Description of the Related Art
Processing defects in static random access memory (SRAM) and dynamic random access memory (DRAM) devices can significantly reduce the processing yield in large scale memory arrays. In order to improve the processing yield of memory chips, various methods of error correction have been created. These include xe2x80x98softxe2x80x99 error correcting whereby software corrects for physical defects, and xe2x80x98hardxe2x80x99 error correcting whereby defective circuit elements are replaced with redundant elements included on the chip. The use of soft or hard error correcting can result in lower chip manufacturing costs and earlier introduction of new products on existing wafer fabrication lines or in new process technologies.
Yield enhancement by xe2x80x98hardxe2x80x99 error correcting on a memory chip is typically produced by including redundant rows and/or columns within the memory array. A few redundant rows or columns can significantly enhance yield of a memory circuit since many devices are rejected for single bit failure or failures in a single row or column. These redundant rows or columns can be added to the memory design to replace defective rows or columns which are identified at electrical test after wafer processing.
To replace a defective memory row or column, the defective row or column is first disconnected from the array. This is accomplished by one of three methods: current blown fuses, laser blown fuses, and laser annealed resistor connections. Then a redundant row or column is enabled and programmed with the defective row or column address.
Although this use of redundant rows and columns of memory cells increases product yield, the additional number of redundant columns/rows of memory cells necessary to bypass a number of defects noticeably increases the amount of silicon space devoted to the redundant columns/rows. Based upon the foregoing, there is a need for replacing defective memory cells without substantially increasing layout size and/or circuit overhead.
The present invention overcomes the shortcomings in prior memory devices and satisfies a significant need for a memory device that more efficiently bypasses defective memory cells in the memory device. According to a preferred embodiment of the present invention, a memory device includes an array of memory cells organized into rows and columns of memory cells. Each row of memory cells includes one or more redundant memory cells. The array of memory cells includes row lines and column lines, with each row line being coupled to memory cells in a distinct row of memory cells and each column line being coupled to memory cells in a distinct column of memory cells, and column input/output lines. The memory device further includes an address decoder for receiving an address value during a memory access operation, selecting a row of memory cells and a coupling a plurality of column input/output lines to the data input/output terminals of the memory device, based upon the received address value. The memory device includes redundancy circuitry for selectively coupling column lines to column input/output lines of the array of memory cells and selectively decoupling at least one column line from the column input/output lines, based upon the received address value. In this way, the redundancy circuitry is capable of selectively decoupling from the column input/output lines a column line associated with a defective memory cell, and coupling to the column input/output lines a column line associated with a redundant memory cell.